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independent clock dual hotlink ii? serializer cyv15g0203tb cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-02105 rev. *c revised may 2, 2007 features ? second-generation hotlink ? technology ? compliant to smpte 292m and smpte 259m video standards ? dual-channel video serializer ? 195- to 1500-mbps serial data signaling rate ? simultaneous operation at different signaling rates ? supports half-rate and full-rate clocking ? internal phase-locked loops (plls) with no external pll components ? redundant differential pecl-compatible serial outputs per channel ? no external bias resistors required ? signaling-rate controlled edge-rates ? internal source termination ? synchronous lvttl parallel interface ? jtag boundary scan ? built-in self-test (bist) for at-speed link testing ? low-power 1.4w @ 3.3v typical ? single 3.3v supply ? thermally enhanced bga ? pb-free package option available ?0.25 bicmos technology functional description the cyv15g0203tb independent clock dual hotlink ii? serializer is a point-to-point or point-to-multipoint communica- tions building block enabling transfer of data over a variety of high-speed serial links including smpte 292m and smpte 259m video applications. it supports signaling rates in the range of 195 to 1500 mbps per serial link. the two channels are independent and can simultaneously operate at different rates. each channel accepts 10-bit parallel characters in an input register and converts them to serial data. figure 1 illus- trates typical connections between independent video co-processors and corresponding cyv15g0203tb serializer and cyv15g0204rb reclocking deserializer chips. the cyv15g0203tb satisfies the smpte-259m and smpte-292m compliance as per smpte eg34-1999 patho- logical test requirements. as a second-generation hotlink device, the cyv15g0203tb extends the hotlink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, and bist) with other hotlink devices. each channel of the cyv15g0203tb dual hotlink ii device accepts scrambled 10-b it transmission characters. these characters are serialized and output from dual positive ecl (pecl) compatible differential transmission-line drivers at a bit-rate of eit her 10- or 20-times the input reference clock for that channel. each channel contains an independent bist pattern generator. this bist hardware allows at-speed testing of the high-speed serial data paths in each transmit section of this device, each receive section of a connected hotlink ii device, and across the interconnecting links. the cyv15g0203tb is ideal for smpte applications where different data rates and serial interface standards are necessary for each channel. some applications include multi-format routers, switc hers, format converters, and cameras. figure 1. hotlink ii? system connections video coprocessor 10 10 video coprocessor 10 10 serial links independent cyv15g0203tb independent reclocking deserializer serializer channel cyv15g0204rb channel reclocked output reclocked output [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 2 of 20 cyv15g0203tb serializer logic block diagram x10 serializer tx txda[9:0] outa1 outa2 phase align buffer refclka x10 serializer tx txdb[9:0] outb1 outb2 phase align buffer refclkb [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 3 of 20 shifter serializer path block diagram txratea input register phase-align buffer spdsela refclka+ refclka? transmit pll clock multiplier txclka bit-rate clock a character-rate clock a outa1+ outa1? outa2+ outa2? phase-align buffer transmit pll clock multiplier a oe[2..1]a txcksela = internal signal txerra txclkoa txda[9:0] 10 10 pabrsta oe[2..1]a 1 0 bist lfsr 10 txbista 10 shifter txrateb input register phase-align buffer spdselb refclkb+ refclkb? transmit pll clock multiplier txclkb bit-rate clock b character-rate clock b outb1+ outb1? outb2+ outb2? phase-align buffer transmit pll clock multiplier b oe[2..1]b txckselb txerrb txclkob txdb[9:0] 10 10 pabrstb oe[2..1]b 1 0 bist lfsr 10 txbistb 10 reset wren addr[2:0] data[3:0] jtag and device configuration and control block diagram = internal signal txrate[a..b] txcksel[a..b] txbist[a..b] oe[2..1][a..b] pabrst[a..b] device configuration and control interface jtag boundary scan controller tdo tms tclk tdi trst reset [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 4 of 20 pin configuration (top view) [1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a nc nc nc nc v cc nc out b1? gnd gnd out b2? gnd out a1? gnd gnd out a2? v cc v cc nc v cc nc b v cc nc v cc nc v cc v cc out b1+ gnd nc out b2+ nc out a1+ gnd nc out a2+ v cc nc nc nc nc c tdi tms v cc v cc v cc nc nc gnd nc nc data [2] data [0] gnd nc spd selb v cc nc trst gnd tdo d tclk reset v cc v cc v cc v cc nc gnd gnd data [3] data [1] gnd gnd gnd nc v cc nc nc scan en2 tmen3 e v cc v cc v cc v cc v cc v cc v cc v cc f nc nc v cc nc nc nc nc nc g gnd wren gnd gnd nc nc spd sela nc h gnd gnd gnd gnd gnd gnd gnd gnd j gnd gnd gnd gnd nc nc nc nc k nc nc gnd gnd nc nc nc nc l nc nc nc gnd nc nc nc gnd m nc nc nc nc nc nc nc gnd n gnd gnd gnd gnd gnd gnd gnd gnd p nc nc nc nc gnd gnd gnd gnd r nc nc nc nc v cc v cc v cc v cc t v cc v cc v cc v cc v cc v cc v cc v cc u tx db[0] tx db[1] tx db[2] tx db[9] v cc nc nc gnd tx da[9] addr [0] ref clkb? tx da[1] gnd tx da[4] tx da[8] v cc nc v cc nc nc v tx db[3] tx db[4] tx db[8] nc v cc nc nc gnd nc gnd ref clkb+ tx clkoa gnd tx da[3] tx da[7] v cc nc nc nc nc w tx db[5] tx db[7] nc nc v cc nc nc gnd addr [2] addr [1] nc tx erra gnd tx da[2] tx da[6] v cc nc ref clka+ nc nc y tx db[6] tx clkb nc nc v cc nc nc gnd tx clkob nc tx clka nc gnd tx da[0] tx da[5] v cc tx errb ref clka? nc nc note 1. nc = do not connect. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 5 of 20 pin configuration (bottom view) [1] 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a nc v cc nc v cc v cc out a2? gnd gnd out a1? gnd out b2? gnd gnd out b1? nc v cc nc nc nc nc b nc nc nc nc v cc out a2+ nc gnd out a1+ nc out b2+ nc gnd out b1+ v cc v cc nc v cc nc v cc c tdo gnd trst nc v cc spd selb nc gnd data [0] data [2] nc nc gnd nc nc v cc v cc v cc tms tdi d tmen3 scan en2 nc nc v cc nc gnd gnd gnd data [1] data [3] gnd gnd nc v cc v cc v cc v cc reset tclk e v cc v cc v cc v cc v cc v cc v cc v cc f nc nc nc nc nc v cc nc nc g nc spd sela nc nc gnd gnd wren gnd h gnd gnd gnd gnd gnd gnd gnd gnd j nc nc nc nc gnd gnd gnd gnd k nc nc nc nc gnd gnd nc nc l gndncncnc gnd nc nc nc m gndncncnc nc nc nc nc n gnd gnd gnd gnd gnd gnd gnd gnd p gnd gnd gnd gnd nc nc nc nc r v cc v cc v cc v cc nc nc nc nc t v cc v cc v cc v cc v cc v cc v cc v cc u nc nc v cc nc v cc tx da[8] tx da[4] gnd tx da[1] ref clkb? addr [0] tx da[9] gnd nc nc v cc tx db[9] tx db[2] tx db[1] tx db[0] v nc nc nc nc v cc tx da[7] tx da[3] gnd tx clkoa ref clkb+ gnd nc gnd nc nc v cc nc tx db[8] tx db[4] tx db[3] w nc nc ref clka+ nc v cc tx da[6] tx da[2] gnd tx erra nc addr [1] addr [2] gnd nc nc v cc nc nc tx db[7] tx db[5] y nc nc ref clka? tx errb v cc tx da[5] tx da[0] gnd nc tx clka nc tx clkob gnd nc nc v cc nc nc tx clkb tx db[6] [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 6 of 20 pin definitions cyv15g0203tb dual hotlink ii serializer name i/o characteristics signal description transmit path data and status signals txda[9:0] txdb[9:0] lvttl input, synchronous, sampled by the associated txclkx or refclkx [2] transmit data inputs . txdx[9:0] data inputs are captured on the rising edge of the transmit interface clock. th e transmit interface clock is selected by the txckselx latch via the device configuration interface. txerra txerrb lvttl output, synchronous to refclkx [3] , asynchronous to transmit channel enable / disable, asynchronous to loss or return of refclkx transmit path error . txerrx is asserted high to indicate detection of a transmit phase-align buffer underflow or overflow . if an underflow or overflow condition is detected, txerrx, for the channel in error, is asserted high and remains asserted until the transmit phase-align buffer is re -centered with the pabrstx latch via the device configuration interface. when txbi stx = 0, the bist progress is presented on the associated txerrx output. the txerrx signal pulses high for one transmit-character clock period to indica te a pass through the bist sequence once every 511 character times. txerrx is also asserted high, when any of the following conditions is true: ? the txpll for the associated channel is powered down. this occurs when oe2x and oe1x for a given channel are both disabl ed by setting oe2x = 0 and oe1x = 0. ? the absence of the refclkx signal. transmit path clock signals refclka refclkb differential lvpecl or single-ended lvttl input clock reference clock . refclkx clock inputs are used as the timing references for the associated transmit pll. these input cl ocks may also be selected to clock the transmit parallel interface. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or complement refclkx input, and leave the alternate refc lkx input open (floating). when driven by an lvpecl clock source, the clock must be a differential clock, using both inputs. txclka txclkb lvttl clock input, internal pull-down transmit path input clock . when configuration latch txckselx = 0, the associated txclkx input is selected as the character- rate input clock for the txdb[9:0] input. in this mode, the txclkx input must be fr equency-coherent to its associated txclkox output clock, but may be offset in phase by any amount. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phas e align buffer, txerrx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx input clock relative to it s associated refclkx is initialized when the configuration latch pabrstx is written as 0. when the associated txerrx is deasserted, the phas e align buffer is initialized and input characters are correctly captured. txclkoa txclkob lvttl output transmit clock output . txclkox output clock is synthesized by each channel?s transmit pll and operates synchronous to the internal transmit character clock. txclkox operates at either the same frequency as refclkx (txratex = 0), or at twice the frequency of refclkx (txr atex = 1). the transmit clock outputs have no fixed phase relationship to refclkx. device control signals reset lvttl input, asynchronous, internal pull-up asynchronous device reset . reset initializes all state machines, counters, and configuration latches in the de vice to a known state. reset must be asserted low for a minimum pulse width. when the reset is removed, all state machines, counters and configuration latches are at an initial st ate. as per the jtag specifications the device reset cannot reset the jtag controlle r. therefore, the jtag controller has to be reset separately. refer to ?jtag support? on page 10 for the methods to reset the jtag state machine. see table 2 on page 10 for the initialize values of the device configuration latches. notes 2. when refclkx is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges o f the associated refclkx. 3. when refclkx is configured for half-rate operation, these outputs are presented relative to both the rising and falling edge s of the associated refclkx. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 7 of 20 spdsela spdselb 3-level select [4] static control input serial rate select . the spdselx inputs specify the operating signaling-rate range of each channel?s pll. low = 195?400 mbd mid = 400?800 mbd high = 800?1500 mbd. device configuration and control bus signals wren lvttl input, asynchronous, internal pull-up control write enable . the wren input writes the values of the data[3:0] bus into the latch specified by the address location on the addr[2:0] bus. [5] addr[2:0] lvttl input asynchronous, internal pull-up control addressing bus . the addr[2:0] bus is the input address bus used to configure the device. the wren input writes the values of the data[3:0] bus into the latch specified by the address location on the addr[2:0] bus. [5] table 2 on page 10 lists the configuration latches within the de vice, and the initialization value of the latches upon the assertion of reset . table 3 on page 11 shows how the latches are mapped in the device. data[3:0] lvttl input asynchronous, internal pull-up control data bus . the data[3:0] bus is the input data bus used to configure the device. the wren input writes the values of the data[3:0] bus into the latch specified by address loca tion on the addr[2:0] bus. [5] table 2 on page 10 lists the configuration latches within the device, and th e initialization value of the latches upon the assertion of reset . table 3 on page 11 shows how the latches are mapped in the device. internal device configuration latches txcksel[a..b] internal latch [6] transmit clock select . txrate[a..b] internal latch [6] transmit pll clock rate select . txbist[a..b] internal latch [6] transmit bist disabled . oe2[a..b] internal latch [6] differential serial output driver 2 enable . oe1[a..b] internal latch [6] differential serial output driver 1 enable . pabrst[a..b] internal latch [6] transmit clock phase alignment buffer reset . factory test modes scanen2 lvttl input, internal pull-down factory test 2. scanen2 input is for factory testing only. this input may be left as a no connect, or gnd only. tmen3 lvttl input, internal pull-down factory test 3 . tmen3 input is for factory testing only. this input may be left as a no connect, or gnd only. analog i/o outa1 outb1 cml differential output primary differential serial data output . the outx1 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl-compatible connections. outa2 outb2 cml differential output secondary differential serial data output . the outx2 pecl-compatible cml outputs (+3.3v referenced) are capable of drivi ng terminated transmissio n lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl-compatible connec- tions. pin definitions (continued) cyv15g0203tb dual hotlink ii serializer name i/o characteristics signal description notes 4. 3-level select inputs are used for static configuration. these are ternary inputs that make use of logic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually implemented by direct connection to v cc (power). the mid level is usually implemented by not connecting the input (left floating), wh ich allows it to self bias to the proper level. 5. see ?device configuration and control interface? on page 9 for detailed information on the operation of the configuration interface. 6. see ?device configuration and control interface? on page 9 for detailed information on the internal latches. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 8 of 20 cyv15g0203tb hotlink ii operation the cyv15g0203tb is a highly configurable, independent clocking, dual-channel serializer, designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple desti- nations. this device supports two 10-bit channels. cyv15g0203tb transmit data path input register the parallel input bus txdx[9:0] can be clocked in using txclkx (txckselx = 0) or refclkx (txckselx = 1). phase-align buffer data from each input register is passed to the associated phase-align buffer, when the txdx[9:0] input registers are clocked using txclkx (txckselx = 0 and txratex = 0). when the txdx[9:0] input registers are clocked using refclkx (txckselx = 1) and refclkx is a full-rate clock, the associated phase a lignment buffer in the transmit path is bypassed. these buffers are used to absorb clock phase differences between the txclkx input clock and the internal character clock for that channel. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phase align buffer, txerrx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx relative to its associated internal character rate clock is initialized when the configuration latch pabrstx is written as 0. when the associated txe rrx is deasserted, the phase align buffer is initialized and input characters are correctly captured. if the phase offset, between the initialized location of the input clock and refclkx, exceeds the skew handling capabilities of the phase-align buffer, an error is reported on that channel?s txerrx output. this output indicates an error continuously until the phase-align buffer for that channel is reset. while the error remains active, the transmitter for that channel outputs a continuous ?1001111000? character (lsb first) to indicate to the remote receiver that an error condition is present in the link. transmit bist each channel contains an internal pattern generator that can be used to validate both the li nk and device operation. these generators are enabled by the associated txbistx latch via the device configuration interfac e. when enabled, a register in the associated channel becomes a signature pattern generator by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character sequence. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached receiver(s). a device reset (reset sampled low) presets the bist enable latches to disable bist on both channels. all data present at the associated txdx[9:0] inputs are ignored when bist is active on that channel. transmit pll clock multiplier each transmit pll clock multip lier accepts a character-rate or half-character-rate external clock at the associated refclkx input, and that clock is multiplied by 10 or 20 (as selected by txratex) to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as txclkox. each clock multiplier pll can accept a refclkx input between 19.5 mhz and 150 mhz, however, this clock range is limited by the operating mode of the cyv15g0203tb clock multiplier (txratex) and by the level on the associated spdselx input. spdselx are 3-level select [4] inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel. the serial signaling-rate and allowable range of refclkx frequencies are listed in table 1 on page 9 . jtag interface tms lvttl input, internal pull-up test mode select . used to control access to the jt ag test modes. if maintained high for 5 tclk cycles, the jtag test controller is reset. tclk lvttl input, internal pull-down jtag test clock . tdo 3-state lvttl output test data out . jtag data output buffer. high-z while jtag test mode is not selected. tdi lvttl input, internal pull-up test data in . jtag data input port. trst lvttl input, internal pull-up jtag reset signal . when asserted (low), this input asynchronously resets the jtag test access port controller. power v cc +3.3v power . gnd signal and power ground for all internal circuits . pin definitions (continued) cyv15g0203tb dual hotlink ii serializer name i/o characteristics signal description [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 9 of 20 the refclkx inputs are differential inputs with each input internally biased to 1.4v. if the refclkx+ input is connected to a ttl, lvttl, or lvcmos clock source, the input signal is recognized when it passes through the internally biased reference point. when driven by a single-ended ttl, lvttl, or lvcmos clock source, connec t the clock source to either the true or complement refclkx input, and leave the alternate refclkx input open (floating). when both the refclkx+ and refclkx? inputs are connected, the clock source must be a differential clock. this can either be a differential lvpecl clock that is dc-or ac-coupled or a differential lvttl or lvcmos clock. by connecting the refclkx? input to an external voltage source, it is possible to adjust the reference point of the refclkx+ input for alternate logic levels. when doing so, it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for 50 transmission lines. these drivers accept data from the transmit shifter, which shifts the data out lsb first. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. transmit channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. note . when a disabled channel (i.e., both outputs disabled) is re-enabled: ? data on the serial outputs may not meet all timing specifi- cations for up to 250 s ? the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used device configuration and control interface the cyv15g0203tb is highly co nfigurable via the configu- ration interface. the configur ation interface allows each channel to be configured independently. table 2 on page 10 lists the configuration latches within the device including the initialization value of the latches upon the assertion of reset . table 3 on page 11 shows how the latches are mapped in the device. each row in the table 3 maps to a 4-bit latch bank. there are 6 such write-only latch banks. when wren = 0, the logic value in the data[3:0] is latched to the latch bank specified by the values in addr[2:0]. the second column of ta b l e 3 specifies the channels associated with the corre- sponding latch bank. for example, the first three latch banks (0,1 and 2) consist of configuration bits for channel a. latch types there are two types of latch banks: static (s) and dynamic (d). each channel is configured by 2 static and 1 dynamic latch banks. the s type contain those settings that normally do not change for a given application, whereas the d type controls the settings that could change during the applicat ion's lifetime. the first and second rows of each channel (address numbers 0, 1, 5, and 6) are the static control latches. the third row of latches for each channel (address numbers 2 and 7) are the dynamic control latches. address numbers 3 and 4 are internal test registers. static latch values there are some latches in the table that have a static value (i.e. 1, 0, or x). the latches that have a ?1? or ?0? must be configured with their corresponding value each time that their associated latch bank is confi gured. the latches that have an ?x? are don?t cares and can be configured with any value. table 1. operating speed settings spdselx txratex refclkx frequency (mhz) signaling rate (mbps) low 1 reserved 195?400 0 19.5?40 mid (open) 1 20?40 400?800 0 40?80 high 1 40?75 800?1500 0 80?150 [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 10 of 20 device configuration strategy the following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. pulse reset low after device power-up. this operation resets both channels. initialize the jtag state machine to its reset state as detailed in the jtag support section. 2. set the static latch banks for the target channel. 3. set the dynamic bank of latches for the target channel. enable the output drivers. [required step.] 4. reset the phase alignment buffer for the target channel. [optional if phase align buffer is bypassed.] jtag support the cyv15g0203tb contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, boundary scan, and bypass are supported. this capability is present only on the lvttl inputs and outputs and the refclkx clock input. the high-speed serial inputs and outputs are not part of the jtag test chain. to ensure valid device operation after power-up (including non-jtag operation), the jtag state machine should also be initialized to a reset state. this should be done in addition to the device reset (using reset). the jtag state machine can be initialized using trst (assertin g it low and de-asserting it or leaving it asserted), or by as serting tms high for at least 5 consecutive tclk cycles. this is necessary in order to ensure that the jtag controller does not enter any of the test modes after device power-up. in this jtag reset state, the rest of the device will be in normal operation. note . the order of device re set (using reset) and jtag initialization does not matter. 3-level select inputs each 3-level select inputs reports as two bits in the scan register. these bits report t he low, mid, and high state of the associated input as 00, 10, and 11 respectively table 2. device configuration and control latch descriptions name signal description txcksela txckselb transmit clock select . the initialization value of the txckselx latch = 1. txckselx selects the clock source used to write data into the transmit input register. when txckselx = 1, the associated input register txdx[9:0] is clocked by refclkx . in this mode, the phase alignment buffer is bypassed. when txckselx = 0, the associated txclkx is used to clock in the input register txdx[9:0]. txratea txrateb transmit pll clock rate select . the initialization value of the txratex latch = 0. txratex is used to select the clock multip lier for the transmit pll. when txrate x = 0, each transmit pll multiples the associated refclkx input by 10 to generate t he serial bit-rate clock. when txratex = 0, the txclkox output clocks are full-rate clocks and follo w the frequency and duty cycle of the associated refclkx input. when txratex = 1, each transmit p ll multiplies the associated refclkx input by 20 to generate the serial bit-rate clock. when tx ratex = 1, the txclkox out put clocks are twice the frequency rate of the refclkx input. when txclkselx = 1 and txratex = 1, the transmit data inputs are captured using both the rising and falling edges of refclkx. txratex = 1 and spdselx = low, is an invalid state and this combination is reserved. txbista txbistb transmit bist disabled . the initialization value of the txbistx latch = 1. txbist x selects if the transmit bist is disabled or enabled. when txbistx = 1, the transmit bist function is disabled. when txbistx = 0, the transmit bist function is enabled. oe2a oe2b secondary differential serial data output driver enable . the initialization value of the oe2x latch = 0. oe2x selects if the out2x secondary differential output drivers are enabled or disabled. when oe2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when oe2x = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is in ternally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. oe1a oe1b primary differential serial data output driver enable . the initialization value of the oe1x latch = 0. oe1x selects if the out1x primary differential out put drivers are enabled or disabled. when oe1x = 1, the associated serial data output driver is enabled allo wing data to be transmitted from the transmit shifter. when oe1x = 0, the associated serial data output driv er is disabled. when a driver is disabled via the configuration interface, it is inte rnally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated in ternal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. pabrsta pabrstb transmit clock phase alignment buffer reset . the initialization value of the pabrstx latch = 1. the pabrstx is used to re-center the transmit phase a lign buffer. when the configuration latch pabrstx is written as a 0, the phase of the txclkx input clock relative to its associated refclkx+/- is initialized. pabrst is an asynchronous input, but is sampled by each txclkx to synchronize it to the internal clock domain. pabrstx is a self clear ing latch. this eliminates the requi rement of writing a 1 to complete the initialization of the phase alignment buffer. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 11 of 20 jtag id the jtag device id for the cyv15g0203tb is ?0c810069?x. table 3. device control latch configuration table addr channel type data3 data2 data1 data0 reset value 0 (000b) a s x x 0 x 1111 1 (001b) a s x 0 txcksela txratea 0110 2 (010b) a d txbista oe2a oe1a pabrsta 1001 9 (101b) b s x x 0 x 1111 10 (110b) b s x 0 txckselb txrateb 0110 11 (111b) b d txbistb oe2b oe1b pabrstb 1001 [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 12 of 20 maximum ratings above which the useful life may be impaired. user guidelines only, not tested storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +3.8v dc voltage applied to lvttl outputs in high-z state .......................................?0.5v to v cc + 0.5v output current into lvttl outputs (low)..................60 ma dc input voltage....................................?0.5v to v cc + 0.5v static discharge voltage.......................................... > 2000 v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma power-up requirements the cyv15g0203tb requires one power-supply. the voltage on any input or i/o pin cannot exceed the power pin during power-up. operating range range ambient temperature v cc commercial 0c to +70c +3.3v 5% cyv15g0203tb dc electrical characteristics parameter description test conditions min. max. unit lvttl-compatible outputs v oht output high voltage i oh = ? 4 ma, v cc = min. 2.4 v v olt output low voltage i ol = 4 ma, v cc = min. 0.4 v i ost output short circuit current v out = 0v [7] , v cc = 3.3v ?20 ?100 ma i ozl high-z output leakage current v out = 0v, v cc ?20 20 a lvttl-compatible inputs v iht input high voltage 2.0 v cc + 0.3 v v ilt input low voltage ?0.5 0.8 v i iht input high current refclkx input, v in = v cc 1.5 ma other inputs, v in = v cc +40 a i ilt input low current refclkx input, v in = 0.0v ?1.5 ma other inputs, v in = 0.0v ?40 a i ihpdt input high current with internal pull-down v in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v ?200 a lvdiff inputs: refclkx v diff [8] input differential voltage 400 v cc mv v ihhp highest input high voltage 1.2 v cc v v illp lowest input low voltage 0.0 v cc /2 v v comref [9] common mode range 1.0 v cc ? 1.2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v i ihh input high current v in = v cc 200 a i imm input mid current v in = v cc /2 ?50 50 a i ill input low current v in = gnd ?200 a differential cml serial outputs: outa1 , outa2 , outb1 , outb2 , outc1 , outc2 , outd1 , outd2 v ohc output high voltage (v cc referenced) 100 differential load v cc ? 0.5 v cc ? 0.2 v 150 differential load v cc ? 0.5 v cc ? 0.2 v notes 7. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 8. this is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. a logic-1 exists when the true (+) input is more positive than the complement ( ? ) input. a logic-0 exists when the complement ( ? ) input is more positive than true (+) input. 9. the common mode range defines the allowable range of refclkx+ and refclkx ? when refclkx+ = refclkx ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 13 of 20 v olc output low voltage (v cc referenced) 100 differential load v cc ? 1.4 v cc ? 0.7 v 150 differential load v cc ? 1.4 v cc ? 0.7 v v odif output differential voltage |(out+) ? (out ? )| 100 differential load 450 900 mv 150 differential load 560 1000 mv power supply typ. max. i cc [10,11] max power supply current refclkx = max commercial 435 530 ma i cc [10,11] typical power supply current refclkx = 125 mhz commercial 425 520 ma cyv15g0203tb dc electrical characteristics (continued) parameter description test conditions min. max. unit ac test loads and waveforms 2.0v 0.8v gnd 2.0v 0.8v 80% 20% 80% 20% r l (includes fixture and probe capacitance) 3.0v v th =1.4v 270 ps 270 ps [13] v th =1.4v 3.3v r1 r2 r1 = 590 r2 = 435 (includes fixture and probe capacitance) c l 7 pf (a) lvttl output test load r l = 100 (b) cml output test load c l (c) lvttl input test waveform (d) cml/lvpecl input test waveform 1ns 1 ns v ihe v ile v ihe v ile [12] [12] cyv15g0203tb ac electrical characteristics parameter description min. max. unit cyv15g0203tb transmitter lvtt l switching characteristics over the operating range f ts txclkx clock cycle frequency 19.5 150 mhz t txclk txclkx period=1/f ts 6.66 51.28 ns t txclkh [14] txclkx high time 2.2 ns t txclkl [14] txclkx low time 2.2 ns t txclkr [14, 15, 16, 17] txclkx rise time 0.2 1.7 ns t txclkf [14, 15, 16, 17] txclkx fall time 0.2 1.7 ns t txds transmit data set-up time to txclkx (txckselx = 0) 2.2 ns t txdh transmit data hold time from txclkx (txckselx = 0) 1.0 ns f tos txclkox clock frequency = 1x or 2x refclkx frequency 19.5 150 mhz t txclko txclkox period = 1/f tos 6.66 51.28 ns t txclkod txclko duty cycle center ed at 60% high time ?1.9 0 ns notes 10. maximum i cc is measured with v cc = max, t a = 25c, with both channels and serial line drivers enabl ed, sending a continuous alternating 01 pattern, and outputs unloaded. 11. typical i cc is measured under similar conditions except with v cc = 3.3v, t a = 25c, with both channels enabled and one serial line driver per channel sending a continuous alternating 01 pattern. the redundant outputs on each channel are powered down. 12. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only. 13. the lvttl switching threshold is 1.4v. all timing references are made relative to where the signal edges cross the threshold voltage. 14. tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 15. the ratio of rise time to falling time must not vary by greater than 2:1. 16. for a given operating frequency, neither rise or fall specific ation can be greater than 20% of the clock-cycle period or the data sheet maximum time. 17. all transmit ac timing parameters measured with 1 ns typical rise time and fall time. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 14 of 20 cyv15g0203tb refclkx switching characteristics over the operating range f ref refclkx clock frequency 19.5 150 mhz t refclk refclkx period = 1/f ref 6.6 51.28 ns t refh refclkx high time (txratex = 1)(half rate) 5.9 ns refclkx high time (txratex = 0)(full rate) 2.9 [14] ns t refl refclkx low time (txratex = 1)(half rate) 5.9 ns refclkx low time (txratex = 0)(full rate) 2.9 [14] ns t refd [18] refclkx duty cycle 30 70 % t refr [14, 15, 16, 17] refclkx rise time (20%?80%) 2 ns t reff [14, 15, 16, 17] refclkx fall time (20%?80%) 2 ns t trefds transmit data set-up time to refclkx - full rate (txratex = 0, txckselx = 1) 2.4 ns transmit data set-up time to refclkx - half rate (txratex = 1, txckselx = 1) 2.3 ns t trefdh transmit data hold time from refclkx - full rate (txratex = 0, txckselx = 1) 1.0 ns transmit data hold time from refclkx - half rate (txratex = 1, txckselx = 1) 1.6 ns cyv15g0203tb bus configuration write timing characteristics over the operating range t datah bus configuration data hold 0 ns t datas bus configuration data setup 10 ns t wrenp bus configuration wren pulse width 10 ns cyv15g0203tb jtag test clock characteristics over the operating range f tclk jtag test clock frequency 20 mhz t tclk jtag test clock period 50 ns cyv15g0203tb device reset characteristics over the operating range t rst device reset pulse width 30 ns cyv15g0203tb transmit serial outputs and tx pll characteristics over the operating range parameter description condition min. max. unit t b bit time 5128 660 ps t rise [14] cml output rise time 20 ? 80% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps t fall [14] cml output fall time 80 ? 20% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps cyv15g0203tb ac electrical characteristics (continued) parameter description min. max. unit note 18. the duty cycle specification is a simultaneous condition with the t refh and t refl parameters. this means that at faster character rates the refclkx duty cycle cannot be as large as 30%?70%. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 15 of 20 pll characteristics parameter description condition min. typ. max. unit cyv15g0203tb transmitter pll characteristics t jtgensd [14, 19] transmit jitter generation - sd data rate refclkx = 27 mhz 200 ps t jtgenhd [14, 19] transmit jitter generation - hd data rate refclkx = 148.5 mhz 76 ps t txlock transmit pll lock to refclkx 200 s capacitance [14] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 4 pf cyv15g0203tb hotlink ii transmitter switching waveforms notes 19. while sending bist data at the corresponding data rate, after 10,000 histogram hits on a digital sampling oscilloscope, time referenced to refclkx input. 20. when refclkx is configured for half-rate operation (txratex = 1) and data is captured using refclkx instead of a txclkx clo ck. data is captured using both the rising and falling edges of refclkx. txclkx t txdh t txds t txclk t txclkh t txclkl transmit interface write timing txclkx selected txdx[9:0] refclkx transmit interface t refclk t refh t refl t trefds t trefdh write timing txratex = 0 txdx[9:0] refclkx selected t trefdh transmit interface write timing txratex = 1 refclkx t refclk t refl t refh note 20 txdx[9:0] t trefds t trefds t trefdh refclkx selected [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 16 of 20 cyv15g0203tb hotlink ii transmitter switching waveforms (continued) txclkox t txclko transmit interface txclkox timing txratex = 1 (internal) refclkx t refclk t refl t refh note 21 note 22 txclkox t txclko transmit interface txclkox timing refclkx note 21 note 22 t refclk t refh t refl txratex = 0 t txclko cyv15g0203tb hotlink ii bus configuration switching waveforms addr[2:0] t datas bus configuration write timing data[3:0] wren t datah t wrenp notes 21. the txclkox output remains at the character rate regardless of the state of txratex and does not follow the duty cycle of re fclkx. 22. the rising edge of txclkox output has no dire ct phase relationship to the refclkx input. [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 17 of 20 table 4. package coordinate signal allocation ball id signal name signal type ball id signal name signal type ball id signal name signal type a01 nc no connect c07 nc no connect f17 nc no connect a02 nc no connect c08 gnd ground f18 nc no connect a03 nc no connect c09 nc no connect f19 nc no connect a04 nc no connect c10 nc no connect f20 nc no connect a05 vcc power c11 data[2] lvttl in pu g01 gnd ground a06 nc no connect c12 data[0] lvttl in pu g02 wren lvttl in pu a07 outb1? cml out c13 gnd ground g03 gnd ground a08 gnd ground c14 nc no connect g04 gnd ground a09 gnd ground c15 spdselb 3 -level sel g17 nc no connect a10 outb2? cml out c16 vc c power g18 nc no connect a11 gnd ground c17 nc no connect g19 spdsela 3-level sel a12 outa1? cml out c18 trst lvttl in pu g20 nc no connect a13 gnd ground c19 gnd ground h01 gnd ground a14 gnd ground c20 tdo lvttl 3-s out h02 gnd ground a15 outa2? cml out d01 tclk lvttl in pd h03 gnd ground a16 vcc power d02 reset lvttl in pu h04 gnd ground a17 vcc power d03 vcc power h17 gnd ground a18 nc no connect d04 vcc power h18 gnd ground a19 vcc power d05 vcc power h19 gnd ground a20 nc no connect d06 vcc power h20 gnd ground b01 vcc power d07 nc no connect j01 gnd ground b02 nc no connect d08 gnd ground j02 gnd ground b03 vcc power d09 gnd ground j03 gnd ground b04 nc no connect d10 data[3] lvttl in pu j04 gnd ground b05 vcc power d11 data[1] lvttl in pu j17 nc no connect b06 vcc power d12 gnd ground j18 nc no connect b07 outb1+ cml out d13 gnd ground j19 nc no connect b08 gnd ground d14 gnd ground j20 nc no connect b09 nc no connect d15 nc no connect k01 nc no connect b10 outb2+ cml out d16 vc c power k02 nc no connect b11 nc no connect d17 nc no connect k03 gnd ground b12 outa1+ cml out d18 nc no connect k04 gnd ground b13 gnd ground d19 scanen2 lvttl in pd k17 nc no connect b14 nc no connect d20 tmen3 lvttl in pd k18 nc no connect b15 outa2+ cml out e01 vcc power k19 nc no connect b16 vcc power e02 vcc power k20 nc no connect b17 nc no connect e03 vcc power l01 nc no connect b18 nc no connect e04 vcc power l02 nc no connect b19 nc no connect e17 vcc power l03 nc no connect b20 nc no connect e18 vcc power l04 gnd ground c01 tdi lvttl in pu e19 vcc power l17 nc no connect c02 tms lvttl in pu e20 vcc power l18 nc no connect c03 vcc power f01 nc no connect l19 nc no connect [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 18 of 20 c04 vcc power f02 nc no connect l20 gnd ground c05 vcc power f03 vcc power m01 nc no connect c06 nc no connect f04 nc no connect m02 nc no connect m03 nc no connect u03 txdb[2] lvttl in w03 nc no connect m04 nc no connect u04 txdb[9] lvttl in w04 nc no connect m17 nc no connect u05 vcc power w05 vcc power m18 nc no connect u06 nc no connect w06 nc no connect m19 nc no connect u07 nc no connect w07 nc no connect m20 gnd ground u08 gnd ground w08 gnd ground n01 gnd ground u09 txda[9] lvttl in w09 addr [2] lvttl in pu n02 gnd ground u10 addr [0] lvttl in pu w10 addr [1] lvttl in pu n03 gnd ground u11 refclkb? pecl in w11 nc no connect n04 gnd ground u12 txda[1] lvttl in w12 txerra lvttl out n17 gnd ground u13 gnd ground w13 gnd ground n18 gnd ground u14 txda[4] lv ttl in w14 txda[2] lvttl in n19 gnd ground u15 txda[8] lv ttl in w15 txda[6] lvttl in n20 gnd ground u16 vcc power w16 vcc power p01 nc no connect u17 nc no connect w17 nc no connect p02 nc no connect u18 vcc power w18 refclka+ pecl in p03 nc no connect u19 nc no connect w19 nc no connect p04 nc no connect u20 nc no connect w20 nc no connect p17 gnd ground v01 txdb[3] lvttl in y01 txdb[6] lvttl in p18 gnd ground v02 txdb[4] lvttl in y02 txclkb lvttl in pd p19 gnd ground v03 txdb[8] lvttl in y03 nc no connect p20 gnd ground v04 nc no connect y04 nc no connect r01 nc no connect v05 vcc power y05 vcc power r02 nc no connect v06 nc no connect y06 nc no connect r03 nc no connect v07 nc no connect y07 nc no connect r04 nc no connect v08 gnd ground y08 gnd ground r17 vcc power v09 nc no connect y09 txclkob lvttl out r18 vcc power v10 gnd ground y10 nc no connect r19 vcc power v11 refclkb+ pecl in y11 txclka lvttl in pd r20 vcc power v12 txclkoa lvttl out y12 nc no connect t01 vcc power v13 gnd ground y13 gnd ground t02 vcc power v14 txda[3] lvttl in y14 txda[0] lvttl in t03 vcc power v15 txda[7] lvttl in y15 txda[5] lvttl in t04 vcc power v16 vcc power y16 vcc power t17 vcc power v17 nc no connect y17 txerrb lvttl out t18 vcc power v18 nc no connect y18 refclka? pecl in t19 vcc power v19 nc no connect y19 nc no connect t20 vcc power v20 nc no connect y20 nc no connect u01 txdb[0] lvttl in w01 txdb[5] lvttl in u02 txdb[1] lvttl in w02 txdb[7] lvttl in table 4. package coordinate signal allocation (continued) ball id signal name signal type ball id signal name signal type ball id signal name signal type [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 19 of 20 ? cypress semiconductor corporation, 2002-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. hotlink is a registered trademark and hotlink ii is a trademar k of cypress semiconductor. all product and company names mentioned in this document may be the tr ademarks of their respective holders. ordering information speed ordering code package name package type operating range standard cyv15g0203tb-bgc bl256 256-ball thermally enhanced ball grid array commercial standard CYV15G0203TB-BGXC bl256 pb-free 256-ball th ermally enhanced ball grid array commercial package diagram figure 2. 256-lead l2 ball grid array (27 x 27 x 1.57 mm) bl256 a b 0.15 c 0.15 c 0.97 ref. 0.600.10 1.570.175 c 0.20 min seating plane side view section a-a top view 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y a ?0.15 m c ?0.30 m c ?0.750.15(256x) b a 1.27 bottom view (ball side) a 0.20(4x) top of mold compound to top of balls 26 typ. a1 corner i.d. 0.50 min. 27.000.13 27.000.13 24.13 24.13 a1 corner i.d. r 2.5 max (4x) 12.065 51-85123-*e [+] feedback [+] feedback
cyv15g0203tb document #: 38-02105 rev. *c page 20 of 20 document history page document title: cyv15g0203tb independ ent clock dual hotl ink ii? serializer document number: 38-02105 rev. ecn no. issue date orig. of change description of change ** 246850 see ecn fre new data sheet *a 338721 see ecn sua added pb-free package option availability *b 384307 see ecn agt revised setup and hold times (t txdh , t trefds , t trefdh ) *c 1034145 see ecn ukk added clarification for the nec essity of jtag controller reset and the methods to implement it. [+] feedback [+] feedback

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